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Silicon Labs /BGM220SC12WGA /CMU_S /DPLLREFCLKCTRL

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Interpret as DPLLREFCLKCTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)CLKSEL

CLKSEL=DISABLED

Description

No Description

Fields

CLKSEL

Clock Select

0 (DISABLED): DPLLREFCLK is not clocked

1 (HFXO): HFXO is clocking DPLLREFCLK

2 (LFXO): LFXO is clocking DPLLREFCLK

3 (CLKIN0): CLKIN0 is clocking DPLLREFCLK

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data